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<p>Video Processing Subsystem configuration structure.  
 <a href="struct_x_v___hdmi_rx_ss1___config.html#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a37e2da3cd22cd0df0ebba9a59d2a0fb4"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss1___config.html#a37e2da3cd22cd0df0ebba9a59d2a0fb4">DeviceId</a></td></tr>
<tr class="memdesc:a37e2da3cd22cd0df0ebba9a59d2a0fb4"><td class="mdescLeft">&#160;</td><td class="mdescRight">DeviceId is the unique ID of the device.  <a href="#a37e2da3cd22cd0df0ebba9a59d2a0fb4">More...</a><br/></td></tr>
<tr class="separator:a37e2da3cd22cd0df0ebba9a59d2a0fb4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac34aadaeb0d531c2374d101e6ac1d46c"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss1___config.html#ac34aadaeb0d531c2374d101e6ac1d46c">BaseAddress</a></td></tr>
<tr class="memdesc:ac34aadaeb0d531c2374d101e6ac1d46c"><td class="mdescLeft">&#160;</td><td class="mdescRight"><pre class="fragment"> BaseAddress is the physical base address of the
</pre><p> subsystem address range  <a href="#ac34aadaeb0d531c2374d101e6ac1d46c">More...</a><br/></td></tr>
<tr class="separator:ac34aadaeb0d531c2374d101e6ac1d46c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa06caad7292658282e00a8b8c7ef4bfc"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss1___config.html#aa06caad7292658282e00a8b8c7ef4bfc">HighAddress</a></td></tr>
<tr class="memdesc:aa06caad7292658282e00a8b8c7ef4bfc"><td class="mdescLeft">&#160;</td><td class="mdescRight"><pre class="fragment"> HighAddress is the physical MAX address of the
</pre><p> subsystem address range  <a href="#aa06caad7292658282e00a8b8c7ef4bfc">More...</a><br/></td></tr>
<tr class="separator:aa06caad7292658282e00a8b8c7ef4bfc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a23cb1bc207dcd4b239ff035c3a7dfe45"><td class="memItemLeft" align="right" valign="top">XVidC_PixelsPerClock&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss1___config.html#a23cb1bc207dcd4b239ff035c3a7dfe45">Ppc</a></td></tr>
<tr class="memdesc:a23cb1bc207dcd4b239ff035c3a7dfe45"><td class="mdescLeft">&#160;</td><td class="mdescRight">Supported Pixel per Clock.  <a href="#a23cb1bc207dcd4b239ff035c3a7dfe45">More...</a><br/></td></tr>
<tr class="separator:a23cb1bc207dcd4b239ff035c3a7dfe45"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aac89f80e85d26d55ba1b5e5faf7e22b8"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss1___config.html#aac89f80e85d26d55ba1b5e5faf7e22b8">MaxBitsPerPixel</a></td></tr>
<tr class="memdesc:aac89f80e85d26d55ba1b5e5faf7e22b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum Supported Color Depth.  <a href="#aac89f80e85d26d55ba1b5e5faf7e22b8">More...</a><br/></td></tr>
<tr class="separator:aac89f80e85d26d55ba1b5e5faf7e22b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ade5e3a9f12bcce870ca087356da0097c"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss1___config.html#ade5e3a9f12bcce870ca087356da0097c">DynamicHDR</a></td></tr>
<tr class="memdesc:ade5e3a9f12bcce870ca087356da0097c"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; Maximum FRL Rate Supporte  <a href="#ade5e3a9f12bcce870ca087356da0097c">More...</a><br/></td></tr>
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<tr class="memitem:aad3079f7c61932fca7de4876a008ff29"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss1___config.html#aad3079f7c61932fca7de4876a008ff29">DSC</a></td></tr>
<tr class="memdesc:aad3079f7c61932fca7de4876a008ff29"><td class="mdescLeft">&#160;</td><td class="mdescRight">DSC Supported.  <a href="#aad3079f7c61932fca7de4876a008ff29">More...</a><br/></td></tr>
<tr class="separator:aad3079f7c61932fca7de4876a008ff29"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afce02f1610b14e6a599c142352055d59"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss1___config.html#afce02f1610b14e6a599c142352055d59">AxiLiteClkFreq</a></td></tr>
<tr class="memdesc:afce02f1610b14e6a599c142352055d59"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXI Lite Clock Frequency in Hz.  <a href="#afce02f1610b14e6a599c142352055d59">More...</a><br/></td></tr>
<tr class="separator:afce02f1610b14e6a599c142352055d59"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acf1343cb7b7cef1889fab0eec80f221d"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss1___config.html#acf1343cb7b7cef1889fab0eec80f221d">VideoInterface</a></td></tr>
<tr class="memdesc:acf1343cb7b7cef1889fab0eec80f221d"><td class="mdescLeft">&#160;</td><td class="mdescRight">0 - AXI4S 1 - Native 2 - Native DE video interface  <a href="#acf1343cb7b7cef1889fab0eec80f221d">More...</a><br/></td></tr>
<tr class="separator:acf1343cb7b7cef1889fab0eec80f221d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab720a83810afc9e162b9dda767642b9e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_v___hdmi_rx_ss1___sub_core.html">XV_HdmiRxSs1_SubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss1___config.html#ab720a83810afc9e162b9dda767642b9e">HdcpTimer</a></td></tr>
<tr class="memdesc:ab720a83810afc9e162b9dda767642b9e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#ab720a83810afc9e162b9dda767642b9e">More...</a><br/></td></tr>
<tr class="separator:ab720a83810afc9e162b9dda767642b9e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad5e615d539bd7133bc6df85fcc2a1ecd"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_v___hdmi_rx_ss1___sub_core.html">XV_HdmiRxSs1_SubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss1___config.html#ad5e615d539bd7133bc6df85fcc2a1ecd">Hdcp14</a></td></tr>
<tr class="memdesc:ad5e615d539bd7133bc6df85fcc2a1ecd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#ad5e615d539bd7133bc6df85fcc2a1ecd">More...</a><br/></td></tr>
<tr class="separator:ad5e615d539bd7133bc6df85fcc2a1ecd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab599515b162907cc0c3ddf3005036b72"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_v___hdmi_rx_ss1___sub_core.html">XV_HdmiRxSs1_SubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss1___config.html#ab599515b162907cc0c3ddf3005036b72">Hdcp22</a></td></tr>
<tr class="memdesc:ab599515b162907cc0c3ddf3005036b72"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#ab599515b162907cc0c3ddf3005036b72">More...</a><br/></td></tr>
<tr class="separator:ab599515b162907cc0c3ddf3005036b72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae087a3e8b92106e5e7cebb2d32315c66"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_v___hdmi_rx_ss1___sub_core.html">XV_HdmiRxSs1_SubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss1___config.html#ae087a3e8b92106e5e7cebb2d32315c66">HdmiRx1</a></td></tr>
<tr class="memdesc:ae087a3e8b92106e5e7cebb2d32315c66"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#ae087a3e8b92106e5e7cebb2d32315c66">More...</a><br/></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Video Processing Subsystem configuration structure. </p>
<p>Each subsystem device should have a configuration structure associated that defines the MAX supported sub-cores within subsystem </p>
</div><h2 class="groupheader">Field Documentation</h2>
<a class="anchor" id="afce02f1610b14e6a599c142352055d59"></a>
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          <td class="memname">u32 XV_HdmiRxSs1_Config::AxiLiteClkFreq</td>
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<p>AXI Lite Clock Frequency in Hz. </p>

<p>Referenced by <a class="el" href="xv__hdmirxss1_8h.html#ae7df2cc91e752d61253d9a86462d95ab">XV_HdmiRxSs1_CfgInitialize()</a>, and <a class="el" href="group__v__hdmirxss1.html#ga68409ded8710da27184abfed11fdddbf">XV_HdmiRxSs1_SubcoreInitHdmiRx1()</a>.</p>

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          <td class="memname">UINTPTR XV_HdmiRxSs1_Config::BaseAddress</td>
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<p><pre class="fragment"> BaseAddress is the physical base address of the
</pre><p> subsystem address range </p>

<p>Referenced by <a class="el" href="xv__hdmirxss1_8h.html#ae7df2cc91e752d61253d9a86462d95ab">XV_HdmiRxSs1_CfgInitialize()</a>, and <a class="el" href="group__v__hdmirxss1.html#ga68409ded8710da27184abfed11fdddbf">XV_HdmiRxSs1_SubcoreInitHdmiRx1()</a>.</p>

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          <td class="memname">u16 XV_HdmiRxSs1_Config::DeviceId</td>
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<p>DeviceId is the unique ID of the device. </p>

<p>Referenced by <a class="el" href="xv__hdmirxss1_8h.html#ae7df2cc91e752d61253d9a86462d95ab">XV_HdmiRxSs1_CfgInitialize()</a>.</p>

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          <td class="memname">u32 XV_HdmiRxSs1_Config::DSC</td>
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<p>DSC Supported. </p>

<p>Referenced by <a class="el" href="xv__hdmirxss1_8h.html#ae7df2cc91e752d61253d9a86462d95ab">XV_HdmiRxSs1_CfgInitialize()</a>.</p>

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          <td class="memname">u32 XV_HdmiRxSs1_Config::DynamicHDR</td>
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<p>&lt; Maximum FRL Rate Supporte </p>
<p>Dynamic HDR supported </p>

<p>Referenced by <a class="el" href="xv__hdmirxss1_8h.html#aea595ce7b6a72c3ef581593dc634f693">XV_HdmiRxSs1_DynHDR_DM_Disable()</a>, <a class="el" href="xv__hdmirxss1_8h.html#ac7d12d5726eed2735460f2f7ae91ac68">XV_HdmiRxSs1_DynHDR_DM_Enable()</a>, <a class="el" href="xv__hdmirxss1_8h.html#a42ec2b4dba172edc37040ec1e9ad7590">XV_HdmiRxSs1_DynHDR_GetInfo()</a>, and <a class="el" href="xv__hdmirxss1_8h.html#aa3c4292a7e63691e8d096746c61c79e5">XV_HdmiRxSs1_DynHDR_SetAddr()</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_v___hdmi_rx_ss1___sub_core.html">XV_HdmiRxSs1_SubCore</a> XV_HdmiRxSs1_Config::Hdcp14</td>
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<p>Sub-core instance configuration. </p>

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          <td class="memname"><a class="el" href="struct_x_v___hdmi_rx_ss1___sub_core.html">XV_HdmiRxSs1_SubCore</a> XV_HdmiRxSs1_Config::Hdcp22</td>
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<p>Sub-core instance configuration. </p>

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          <td class="memname"><a class="el" href="struct_x_v___hdmi_rx_ss1___sub_core.html">XV_HdmiRxSs1_SubCore</a> XV_HdmiRxSs1_Config::HdcpTimer</td>
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<p>Sub-core instance configuration. </p>

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          <td class="memname"><a class="el" href="struct_x_v___hdmi_rx_ss1___sub_core.html">XV_HdmiRxSs1_SubCore</a> XV_HdmiRxSs1_Config::HdmiRx1</td>
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<p>Sub-core instance configuration. </p>

<p>Referenced by <a class="el" href="group__v__hdmirxss1.html#ga68409ded8710da27184abfed11fdddbf">XV_HdmiRxSs1_SubcoreInitHdmiRx1()</a>.</p>

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<p><pre class="fragment"> HighAddress is the physical MAX address of the
</pre><p> subsystem address range </p>

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          <td class="memname">u8 XV_HdmiRxSs1_Config::MaxBitsPerPixel</td>
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<p>Maximum Supported Color Depth. </p>

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<p>Supported Pixel per Clock. </p>

<p>Referenced by <a class="el" href="xv__hdmirxss1_8h.html#a4b1da9fb9e5b37bea30c629293a76772">XV_HdmiRxSs1_SetDefaultPpc()</a>, <a class="el" href="xv__hdmirxss1_8h.html#ac95834c8296864ddf9bd11cddee740da">XV_HdmiRxSs1_SetPpc()</a>, <a class="el" href="xv__hdmirxss1_8h.html#a33f9facfc1978f57febcf29682fed6c7">XV_HdmiRxSs1_SetStream()</a>, and <a class="el" href="group__v__hdmirxss1.html#ga68409ded8710da27184abfed11fdddbf">XV_HdmiRxSs1_SubcoreInitHdmiRx1()</a>.</p>

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<p>0 - AXI4S 1 - Native 2 - Native DE video interface </p>

<p>Referenced by <a class="el" href="group__v__hdmirxss1.html#ga68409ded8710da27184abfed11fdddbf">XV_HdmiRxSs1_SubcoreInitHdmiRx1()</a>.</p>

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